NXP Semiconductors i.MX RT500 Crossover Microcontrollers
NXP Semiconductors i.MX RT500 Crossover Microcontrollers are secure embedded MCUs optimized for low-power Human Machine Interface (HMI) applications. The i.MX RT500 MCUs are part of NXP’s EdgeVerse™ edge computing platform. The i.MX RT500 MCUs combine a graphics engine and a streamlined Cadence® Tensilica® Fusion F1 DSP core with an Arm® Cortex®-M33 core, offering an ideal balance of power optimization and high-performance capabilities.The NXP i.MX RT500 MCUs feature up to 5MB SRAM, 2x 32kB FlexSPI cache, and dynamic decryption. These devices also include a wide range of peripherals, including a high-speed USB device/host + PHY, two DMA channels, two SD/eMMC interfaces, a digital microphone interface with up to 8-channels, and up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI, I2C, I2S, or UART. And, with an integrated 2D GPU with Vector Graphics Acceleration and Parallel + LCD Interface + MIPI DS controller, the i.MX RT500 MCUs simplify the development of display-based applications while maintaining low power consumption.
The i.MX RT500 MCU family, part of the NXP EdgeLock Assurance program, offers on-chip security capabilities and is built on a foundation of secure boot, secure debug, and secure life cycle management designed to resist remote and software local attacks.
The NXP Semiconductors i.MX RT500 MCUs are available in a 249 terminal Fan-Out Wafer-Level Package (FOWLP), with a -20°C to +70°C operating temperature range.
Features
- Real-time processing
- Arm Cortex-M33 running up to 200MHz with ultra-fast real-time responsiveness
- Optional Cadence® Tensilica® Fusion F1 DSP running up to 200MHz with a 32x32 MAC
- Cryptography and Math Accelerators for security and complex algorithms
- Up to 5MB on-chip SRAM with zero wait-state access for critical code and data
- Integration
- Optional 2D GPU with display LCD controller and MIPI DSI support
- Quad/Octal SPI Flash and PSRAM memory interface with on-the-fly memory decryption
- USB 2.0 high-speed host and device interface with PHY
- Up to 12x Flexcomms, configurable to SPI/I2C/UART/I2S interfaces; separate I3C and dedicated I2C for PMIC
- Up to 2x SD/eMMC memory card interfaces
- Digital microphone interface supporting up to 8 channels
- Low power
- 28nm FD-SOI process optimized for both active and leakage power
- Low leakage SRAM for extended battery life
- Advanced security
- Secure boot with immutable hardware "root-of-trust"
- SRAM Physically Unclonable Function (PUF) based unique key storage
- Acceleration for symmetric (AES-256 and SHA2-256) and asymmetric cryptography (ECC and RSA)
- Optional fuse-based root key storage mechanism
Applications
- Industrial - exercise equipment
- Mobile
- Hearables
- Smartwatches
- Personal health
- Technologies - IoT
- Smart home
- HMI for small and medium appliances
- Toys and games
Documents
- Datasheets
- Reference Manuals
- Application Notes
Block Diagram
