Analog Devices Inc. AD4083 Low Power Analog-to-Digital Converters
Analog Devices Inc. AD4083 Low Power Analog-to-Digital Converters (ADCs) are high-speed, low-noise, low-distortion, 16-bit, Easy Drive, successive approximation register (SAR) ADCs. These converters operate at 265nVrms low 1/f low-frequency noise (0.1Hz to 10Hz), 70.2mW typical at 40MSPS, low power, 92.94dBFS dynamic range, and 10.69nV/√Hz,165.9dBFS/Hz noise spectral density. The AD4083 ADCs maintain a high-performance Signal-to-Noise and Distortion (SINAD) ratio >90dBFS at signal frequencies in excess of 1MHz. These ADCs feature an integrated, low-drift reference buffer and decoupling, and integrated VCM generation. The Easy Drive reduces both signal-chain complexity and power consumption while enabling greater channel density and greater flexibility in companion-component selection.
The AD4083 includes a low-drift reference buffer, LDO regulators to generate the ADC core and digital interface supply rails, and a 16K result data FIFO. These ADCs are available in 49-ball, 5mm x 5mm CSP_BGA, and 0.65mm-pitch packages with an integrated supply decoupling capacitor. Typical applications include digital imaging, cell analysis, spectroscopy, automated test equipment, radar level measurement, nondestructive testing, and high-speed data acquisition.
Features
- 16-bit resolution, no missing codes
- 40MSPS, 48.43ns conversion latency throughput
- 10.69nV/√Hz,165.9dBFS/Hz noise spectral density
- 265nVrms low 1/f, low frequency noise (0.1Hz to 10Hz)
- 70.2mW typical at 40MSPS low power
- ±8ppm (typical), ±12ppm (maximum) INL
- 92.94dBFS dynamic range
- SNR/THD:
- 92.2dB (typical)/-111dB (typical) at fIN = 1kHz
- 92dB (typical)/-103.4dB (typical) at fIN = 1MHz
- Easy drive:
- 6V p-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current
- Integrated, low-drift reference buffer and decoupling
- Integrated VCM generation
- Digital features and data interface:
- Conversion result FIFO, 16K sample depth
- Digital averaging filter with up to 210 decimation
- SPI configuration
- Configurable data interface:
- Single lane, DDR, serial LVDS, 640Mbps per lane
- Dual lane, DDR, serial LVDS, 320Mbps per lane
- Single/quad lane SPI data interface
- Package:
- 49-ball, 5mm x 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
- −40°C to +85°C operating temperature range
Applications
- Digital imaging
- Cell analysis
- Spectroscopy
- Automated test equipment
- High-speed data acquisition
- Digital control loops, hardware in the loop
- Power quality analysis
- Source measurement units
- Electron and X-ray microscopy
- Radar level measurement
- Nondestructive test
Functional Block Diagram
Typical Applications Diagram
Pin Configurations & Function Descriptions
