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AS4C512M16D3LB-12BIN

Name: Alliance Memory AS4C512M16D3LB-12BIN
Brand: Alliance Memory
SKU: 913-4C51216D3LB12BIN
Price: 213.88 DKK
Availability: InStock

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Mouser No:

913-4C51216D3LB12BIN

Mfr. No:

AS4C512M16D3LB-12BIN

Mfr.:

Alliance Memory
Alliance Memory

Description:

DRAM DDR3L, 8G, 512M X 16, 1.35V, 96-BALL FBGA, 800MHZ INDUSTRIAL TEMP B Die(MT41K512M16HA-125IT:A),

Datasheet:

AS4C512M16D3LB-12BIN Datasheet (PDF)

ECAD Model:

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More Information

Learn more about Alliance Memory AS4C512M16D3LB-12BIN

In Stock: 687

Stock:: 687 Can Dispatch Immediately

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Factory Lead Time:: 4 Weeks Estimated factory production time for quantities greater than shown.

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Pricing (DKK)

Qty.	Unit Price	Ext. Price
	213,88 kr.	213,88 kr.
	197,84 kr.	1.978,40 kr.
	191,57 kr.	4.789,25 kr.
	186,28 kr.	9.314,00 kr.
	178,22 kr.	17.822,00 kr.
	173,59 kr.	31.246,20 kr.

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Alliance Memory
Product Category:	DRAM
RoHS:
Type:	SDRAM - DDR3L
Memory Size:	8 Gbit
Data Bus Width:	16 bit
Maximum Clock Frequency:	800 MHz
Package/Case:	FBGA-96
Organisation:	512 M x 16
Access Time:	20 ns
Supply Voltage - Min:	1.283 V
Supply Voltage - Max:	1.45 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 95 C
Series:	AS4C512M16D3LB-12
Packaging:	Tray
Brand:	Alliance Memory
Moisture Sensitive:	Yes
Mounting Style:	SMD/SMT
Product Type:	DRAM
Factory Pack Quantity:	180
Subcategory:	Memory & Data Storage
Supply Current - Max:	122 mA
Unit Weight:	4,579 g

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Datasheet

AS4C512M16D3LB-12BIN Datasheet (PDF)

CNHTS:: 8542329010
USHTS:: 8542320036
ECCN:: EAR99

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.